This application is based on Japanese Patent Application No. 2002-166621, filed on Jun. 7, 2002, the entire contents of which are incorporated herein by reference.
A) Field of the Invention
The present invention relates to a wiring pattern forming method, and more particularly to a wiring pattern forming method of forming a trench through an insulating layer, depositing a conductive material on the insulating layer to bury the trench with the conductive material, and polishing the conductive material to leave a portion of the conductive material in the trench.
B) Description of the Related Art
A damascene method, which is compatible with both high speed and reliability, is used in the wiring pattern forming process for a high density semiconductor integrated circuit device. A dual damascene method is essential for the manufacture of sophisticated semiconductor integrated circuit devices, which method forms trenches and via holes for a wiring pattern thorough an interlayer insulating film, buries the trenches and via holes with copper and removes an unnecessary portion of the copper by chemical mechanical polishing.
With reference to FIGS. 5A to 5D, a wiring layer forming method using a conventional dual damascene method will be described.
As shown in FIG. 5A, a copper wiring layer 101 is disposed in the partial area of a surface layer of an underlying interlayer insulating film 100. On the interlayer insulating film 100 and wiring layer 101, a cap layer 102, a first interlayer insulating film 103, an etching stopper layer 104 and a second interlayer insulating film 105 are sequentially deposited. A wiring trench 106 is formed through the second interlayer insulating film 105 by an ordinary photolithography process. The etching stopper layer 104 is therefore exposed on the bottom of the wiring trench 106.
As shown in FIG. 5B, an opening is formed through the etching stopper layer 104 exposed on the bottom of the wiring trench 106 by using ordinary photolithography techniques. The first interlayer insulating film 103 is etched via the opening to form a via hole 107. The cap layer 102 exposed on the bottom of the via hole 107 is removed to expose the copper wiring layer 101.
A barrier metal layer is formed on the inner surfaces of the wiring trench 106 and via hole 107, and a copper seed layer is formed on the barrier metal layer. Copper is electroplated by using the seed layer as an electrode to form a copper layer 108. The copper layer 108 is filled in the wiring trench 106 and via hole 107.
As shown in FIG. 5C, the copper layer 108 is subjected to chemical mechanical polishing (CMP) to remove an unnecessary portion of the copper layer 108. The copper wiring layer 108 is therefore left in the wiring trench 106 and via hole 107.
As shown in FIG. 5D, on the second interlayer insulating film 105 and copper wiring layer 108, a cap layer 109 and a third interlayer insulating film 110 are formed. On this wiring layer 108, an upper level wiring layer is formed by a method similar to that used for forming the wiring layer 108.
As CMP of the copper wiring layer 108 is performed at the process shown in FIG. 5C, irregularity called dishing and erosion is formed on the surface of the substrate.
FIG. 6A shows the measurement results of irregularity on a substrate surface after CMP. The abscissa represents a scan distance along the substrate surface and one gradation corresponds to 80 xcexcm. The ordinate represents a surface height and one gradation corresponds to 50 nm. Dishing D is formed at positions corresponding to the copper wiring pattern. Erosion E is formed in the area where copper wires are dense.
Dishing is formed because a polishing pad used for CMP deforms and the motion of the polishing pad follows the wiring pattern. Erosion is formed because a work pressure of CMP is concentrated upon an insulating film separating copper wires so that the insulating film and copper wires are polished excessively.
FIG. 6B shows the relation between a dishing depth and a wiring width. The abscissa represents a wiring width in the unit of xe2x80x9cxcexcmxe2x80x9d and the ordinate represents a dishing depth in the unit of xe2x80x9cnmxe2x80x9d. It can be seen that as the wiring width becomes broader, the dishing becomes deeper.
If dishing and erosion are formed, the surface of the third interlayer insulating film 110 shown in FIG. 5D has irregularity in conformity with the surface irregularity of the underlying layer. Irregularity formed on the surface of an interlayer insulating film may generate copper polishing residues as the copper layer buried in the wiring trench formed through the interlayer insulating film is polished. The copper polished residues may cause a short circuit of wiring lines. In order to prevent the generation of copper polishing residues, it is necessary to planarize the surface of an interlayer insulating film by CMP or the like after it is formed.
It is an object of the invention to provide a wiring pattern forming method capable of suppressing the formation of irregularity such as dishing and erosion.
According to one aspect of the present invention, there is provided a method of forming a wiring layer, comprising the steps of: (a) forming a first insulating film on an underlying substrate, the first insulating film comprising a first insulating material; (b) forming a second insulating film on the first insulating film, the second insulating film comprising a second insulating material different from the first insulating material; (c) forming a trench through the second and first insulating films, the trench reaching at least an intermediate depth of the first insulating film; (d) depositing a wiring layer comprising a conductive material on the second insulating film, the wiring layer burying the trench; (e) polishing the wiring layer to leave the wiring layer in the trench; and (f polishing the wiring layer and the second insulating film until the first insulating film is exposed.
By properly selecting the polishing conditions of the step (f, the formation of dishing and erosion can be suppressed.
As above, irregularity of a substrate surface after chemical mechanical polishing can be reduced.